| 数据搜索系统,热门电子元器件搜索 |
|
H8SX/1663 数据表(PDF) 646 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
H8SX/1663 数据表(HTML) 646 Page - Renesas Technology Corp |
|
646 / 1158 page ![]() Section 11 Programmable Pulse Generator (PPG) Rev.1.00 Jun. 07, 2006 Page 594 of 1102 REJ09B0294-0100 11.4 Operation Figure 11.2 shows a schematic diagram of the PPG. PPG pulse output is enabled when the corresponding bits in NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match. Output trigger signal Pulse output pin Internal data bus Normal output/inverted output C PODR QD NDER Q NDR QD Figure 11.2 Schematic Diagram of PPG 11.4.1 Output Timing If pulse output is enabled, the NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. TCNT N N + 1 P φ TGRA N Compare match A signal NDRH mn PODRH PO8 to PO15 n m n Figure 11.3 Timing of Transfer and Output of NDR Contents (Example) |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |