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Section 12 8-Bit Timers (TMR)

Rev.1.00 Jun. 07, 2006 Page 605 of 1102

REJ09B0294-0100

Section 12 8-Bit Timers (TMR)

This LSI has four units (unit 0 to unit 3) of an on-chip 8-bit timer module that comprise two 8-bit

counter channels, totaling eight channels. The 8-bit timer module can be used to count external

events and also be used as a multifunction timer in a variety of applications, such as generation of

counter reset, interrupt requests, and pulse output with a desired duty cycle using a compare-match

signal with two registers.

Figures 12.1 to 12.4 show block diagrams of the 8-bit timer module (unit 0 to unit 3).

This section describes unit 0 (channels 0 and 1) and unit 2 (channels 4 and 5), both of which have

the same functions. Unit2 and unit 3 can generate baud rate clock for SCI and have the same

functions.

12.1

Features

• Selection of seven clock sources

The counters can be driven by one of six internal clock signals (P

φ/2, Pφ/8, Pφ/32, Pφ/64,

φ/1024, or Pφ/8192) or an external clock input (only internal clock available in units 2 and 3:

φ, Pφ/2, Pφ/8, Pφ/32, Pφ/64, Pφ/1024, and Pφ/8192).

• Selection of three ways to clear the counters

The counters can be cleared on compare match A or B, or by an external reset signal. (This is

available only in unit 0 and unit 1.)

• Timer output control by a combination of two compare match signals

The timer output signal in each channel is controlled by a combination of two independent

compare match signals, enabling the timer to output pulses with a desired duty cycle or PWM

output.

• Cascading of two channels

Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the

lower 8 bits (16-bit count mode).

TMR_1 can be used to count TMR_0 compare matches (compare match count mode).

• Three interrupt sources

Compare match A, compare match B, and overflow interrupts can be requested independently.

(This is available only in unit 0 and unit 1.)

• Generation of trigger to start A/D converter conversion (available in unit 0 and unit 1 only)

• Capable of generating baud rate clock for SCI_5 and SCI_6. (This is available only in unit 2

and unit 3). For details, see section 15, Serial Communication Interface (SCI, IrDA, CRC).

• Module stop state specifiable

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