H8SXSLASH1663 datasheet(681/1158 Pages) RENESAS

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Section 12 8-Bit Timers (TMR)

Rev.1.00 Jun. 07, 2006 Page 629 of 1102

REJ09B0294-0100

(3)

Pin Output

• Control of output from the TMO0 pin by the bits OS3 to OS0 in TCSR_0 is in accordance with

the 16-bit compare match conditions.

• Control of output from the TMO1 pin by the bits OS3 to OS0 in TCSR_1 is in accordance with

the lower 8-bit compare match conditions.

12.6.2

Compare Match Count Mode

When the bits CKS2 to CKS0 in TCR_1 are set to B'100, TCNT_1 counts compare match A for

channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF

flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with

the settings for each channel.

12.7

Interrupt Sources

12.7.1

Interrupt Sources and DTC Activation

• Interrupt in unit 0 and unit 1

There are three interrupt sources for the 8-bit timer (TMR_0 or TMR_1): CMIA, CMIB, and OVI.

Their interrupt sources and priorities are shown in table 12.4. Each interrupt source is enabled or

disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt

requests are sent for each to the interrupt controller. It is also possible to activate the DTC by

means of CMIA and CMIB interrupts (This is available in unit 0 and unit 1 only).

Table 12.4

8-Bit Timer (TMR_0 or TMR_1) Interrupt Sources (in Unit 0 and Unit 1)

Signal

Name

Interrupt Source

Interrupt

Flag

DTC

Activation

Priority

CMIA0

TCORA_0 compare match CMFA

Possible

High

CMIB0

TCORB_0 compare match CMFB

Possible

OVI0

TCNT_0 overflow

OVF

Not possible Low

CMIA1

TCORA_1 compare match CMFA

Possible

High

CMIB1

TCORB_1 compare match CMFB

Possible

OVI1

TCNT_1 overflow

OVF

Not possible Low

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