H8SXSLASH1663 datasheet(684/1158 Pages) RENESAS

部件名	H8SX/1663

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

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制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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684 / 1158 page

Section 12 8-Bit Timers (TMR)

Rev.1.00 Jun. 07, 2006 Page 632 of 1102

REJ09B0294-0100

12.8.3

Conflict between TCNT Write and Increment

If a TCNT input clock pulse is generated during the T

2 state of a TCNT write cycle, the write takes

priority and the counter is not incremented as shown in figure 12.16.

Address

TCNT address

Internal write signal

TCNT input clock

TCNT

TCNT write cycle by CPU

Counter write data

Figure 12.16 Conflict between TCNT Write and Increment

12.8.4

Conflict between TCOR Write and Compare Match

If a compare match event occurs during the T

2 state of a TCOR write cycle, the TCOR write takes

priority and the compare match signal is inhibited as shown in figure 12.17.

Address

TCOR address

Internal write signal

TCNT

TCOR

TCOR write cycle by CPU

TCOR write data

N + 1

Compare match signal

Inhibited

Figure 12.17 Conflict between TCOR Write and Compare Match

H8SX/1663 数据表(PDF) 684 Page - Renesas Technology Corp