H8SXSLASH1663 datasheet(706/1158 Pages) RENESAS

706 / 1158 page

Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Rev.1.00 Jun. 07, 2006 Page 654 of 1102

REJ09B0294-0100

Asynchronous Mode (SCI_0, 1, 2, 4, 5, and 6):

• Data length: 7 or 8 bits

• Stop bit length: 1 or 2 bits

• Parity: Even, odd, or none

• Receive error detection: Parity, overrun, and framing errors

• Break detection: Break can be detected by reading the RxD pin level directly in case of a

framing error

• Enables transfer rate clock input from TMR (SCI_5, SCI_6)

• Average transfer rate generator (SCI_2)

10.667-MHz operation: 115.192 kbps or 460.784 kbps can be selected

16-MHz operation: 115.192 kbps, 460.784 kbps, or 720 kbps can be selected

32-MHz operation: 720 kbps

• Average transfer rate generator (SCI_5, SCI_6)

8-MHz operation: 460.784 kbps can be selected

10.667-MHz operation: 115.152 kbps or 460.606 kbps can be selected

12-MHz operation: 230.263 kbps or 460.526 kbps can be selected

16-MHz operation: 115.196 kbps, 460.784 kbps, 720 kbps, or 921.569 kbps can be selected

24-MHz operation: 115.132 kbps, 460.526 kbps, 720 kbps, or 921.053 kbps can be selected

32-MHz operation: 720 kbps can be selected

Clocked Synchronous Mode (SCI_0, 1, 2, and 4):

• Data length: 8 bits

• Receive error detection: Overrun errors

Smart Card Interface:

• An error signal can be automatically transmitted on detection of a parity error during reception

• Data can be automatically re-transmitted on receiving an error signal during transmission

• Both direct convention and inverse convention are supported

H8SX/1663 数据表(PDF) 706 Page - Renesas Technology Corp