H8SXSLASH1663 datasheet(750/1158 Pages) RENESAS

750 / 1158 page

Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Rev.1.00 Jun. 07, 2006 Page 698 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

IrRxINV

R/W

IrRx Data Invert

This bit specifies the inversion of the logic level in IrRxD

output. When inversion is done, the pulse width of high

state specified by the bits 6 to 4 becomes the pulse

width in low state.

0: Uses the IrRxD input data as it is as receive data.

1: Uses the inverted IrRxD input data as receive data.

1, 0



All 0

—

Reserved

These bits are always read as 0. It should not be set to

15.4

Operation in Asynchronous Mode

Figure 15.5 shows the general format for asynchronous serial communication. One frame consists

of a start bit (low level), transmit/receive data, a parity bit, and stop bits (high level). In

asynchronous serial communication, the communication line is usually held in the mark state

(high level). The SCI monitors the communication line, and when it goes to the space state (low

level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and

receiver are independent units, enabling full-duplex communication. Both the transmitter and the

receiver also have a double-buffered structure, so that data can be read or written during

transmission or reception, enabling continuous data transmission and reception.

LSB

Start

bit

MSB

Idle state

(mark state)

Stop bit

Transmit/receive data

0/1

Serial

data

Parity

bit

1 bit

1 or

2 bits

7 or 8 bits

1 bit,

or none

One unit of transfer data (character or frame)

Figure 15.5 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits)

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