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H8SX/1663R 数据表(PDF) 373 Page - Renesas Technology Corp

部件名 H8SX/1663R
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663R 数据表(HTML) 373 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 341 of 1468
REJ09B0412-0200
(3)
When TRWL = 1
When the SDRAM interface is written to, one Trwl cycle is inserted after the Tc2 cycle. The
DACK and EDACK signals stay asserted until the end of the Trwl cycle. The hold time of data
output from an external device can be extended by one cycle.
Figure 9.87 shows an output timing example of the
DACK and EDACK signals when TRWL = 1
with DDS = 1, EDDS = 1, DKC = 0 and EDKC = 0.
T
p
T
r
T
c1
T
c2
T
rwl
T
c1
T
c2
T
rwl
SDRAM
φ
Address bus
Row address
Column address 2
Column address 1
CS
Precharge-sel
RAS
CAS
WE
CKE
PALL ACTV NOP
NOP
WRIT
WRIT
NOP
DQMLU
DQMLL
D7 to D0
BS
DACK or EDACK
RD/
WR
D15 to D8
Row
address
High
Figure 9.87 Output Timing Example of
DACK and EDACK when TRWL = 1 (Write)



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