H8SXSLASH1663R datasheet(504/1504 Pages) RENESAS

部件名	H8SX/1663R

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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504 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 472 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

value

R/W

Description

4, 3



All 0

Reserved

They are always read as 0 and cannot be modified.

EDMAP2

EDMAP1

EDMAP0

R/W

EXDMA Priority Levels 2 to 0

Selects the EXDMAC priority level when using the CPU

priority control function over DTC and EXDMAC. When

the EXDMAC priority level is lower than the CPU

priority level, EXDMAC masks the acceptance of

transfer source and waits until the CPU priority level

becomes low. The priority level can be set

independently for each channel. This bit is enabled

when the CPUPCE bit in CPUPCR is 1.

000: Priority level 0 (lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (highest)

Note:

Only 0 can be written to these bits after 1 is read to clear the flag.

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