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H8SX/1663R 数据表(PDF) 505 Page - Renesas Technology Corp

部件名 H8SX/1663R
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663R 数据表(HTML) 505 Page - Renesas Technology Corp

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Section 11 EXDMA Controller (EXDMAC)
Rev. 2.00 Sep. 24, 2008 Page 473 of 1468
REJ09B0412-0200
11.3.7
EXDMA Address Control Register (EDACR)
EDACR sets the operating modes and transfer methods.
31
AMS
0
R/W
30
DIRS
0
R/W
29
0
R
28
0
R
27
0
R
24
ARS0
0
R/W
26
RPTIE
0
R/W
25
ARS1
0
R/W
Bit
Bit Name
Initial Value
R/W
23
0
R
22
0
R
21
SAT1
0
R/W
20
SAT0
0
R/W
19
0
R
16
DAT0
0
R/W
18
0
R
17
DAT1
0
R/W
Bit
Bit Name
Initial Value
R/W
15
SARIE
0
R/W
14
0
R
13
0
R
12
SARA4
0
R/W
11
SARA3
0
R/W
8
SARA0
0
R/W
10
SARA2
0
R/W
9
SARA1
0
R/W
Bit
Bit Name
Initial Value
R/W
7
DARIE
0
R/W
6
0
R
5
0
R
4
DARA4
0
R/W
3
DARA3
0
R/W
0
DARA0
0
R/W
2
DARA2
0
R/W
1
DARA1
0
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial
value
R/W
Description
31
AMS
0
R/W
Address Mode Select
Selects single address mode or dual address mode.
When single address mode is selected,
EDACK pin is
valid due to the EDACKE bit setting in EDMDR.
0: Dual address mode
1: Single address mode
30
DIRS
0
R/W
Single Address Direction Select
Specifies the data transfer direction in single address
mode. In dual address mode, the specification by this
bit is ignored.
In cluster transfer mode, the internal cluster buffer will
be the source or destination in place of the external
device with
DACK.
0: EDSAR transferred as a source address
1: EDDAR transferred as a destination address



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