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H8SX/1663R 数据表(PDF) 537 Page - Renesas Technology Corp

部件名 H8SX/1663R
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663R 数据表(HTML) 537 Page - Renesas Technology Corp

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Section 11 EXDMA Controller (EXDMAC)
Rev. 2.00 Sep. 24, 2008 Page 505 of 1468
REJ09B0412-0200
Channel 0
Channel 1
Channel 2
Channel 0 transfer
Channel 1 transfer
Channel 2 transfer
Channel 0
Channel 1
Channel 2
Idle
Idle
Request cleared
Request cleared
Request cleared
Request
held
Request
held
Request
held
Selected
Selected
Not
selected
Address bus
Channel 0
Channel 1
Channel 2
B
φ
EXDMAC
control
Figure 11.22 Example of Channel Priority Timing
11.5.9
Basic Bus Cycles
An example of the basic bus cycle timing is shown in figure 11.23. In this example, word-size
transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus
mastership is transferred from the CPU to the EXDMAC, a source address read and destination
address write are performed. The bus is not released in response to another bus request, etc.,
between these read and write operations. As like CPU cycles, EXDMAC cycles conform to the
bus controller settings.
CPU cycle
EXDMAC cycle (one word transfer)
CPU cycle
Address bus
B
φ
T
1
T
2
T
1
T
2
T
3
T
1
T
2
T
3
Source address
Destination address
RD
LHWR
LLWR
High
Figure 11.23 Example of EXDMA Transfer Bus Timing



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