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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX/1663R 数据表(PDF) 538 Page - Renesas Technology Corp |
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H8SX/1663R 数据表(HTML) 538 Page - Renesas Technology Corp |
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538 / 1504 page  Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Sep. 24, 2008 Page 506 of 1468 REJ09B0412-0200 11.5.10 Bus Cycles in Dual Address Mode (1) Normal Transfer Mode (Cycle Steal Mode) In cycle steal mode, the bus is released after one byte, word, or longword has been transferred. While the bus is released, one CPU, DMAC, or DTC bus cycle is initiated. Figure 11.24 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. EXDMA read EXDMA write Address bus EXDMA read EXDMA write EXDMA read EXDMA write B φ RD LHWR, LLWR ETEND Bus release Last transfer cycle Bus release Bus release Bus release Figure 11.24 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer Figures 11.25 and 11.26 show examples of transfer when ETEND output is enabled, and longword-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. In figure 11.25, the transfer source (SAR) address is not at a longword boundary and the transfer destination (DAR) address is at the longword boundary. In figure 11.26, the transfer source (SAR) address is at the longword boundary and the transfer destination (DAR) address is not at the longword boundary. |
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