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H8SX/1663R 数据表(PDF) 662 Page - Renesas Technology Corp |
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H8SX/1663R 数据表(HTML) 662 Page - Renesas Technology Corp |
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662 / 1504 page ![]() Section 13 I/O Ports Rev. 2.00 Sep. 24, 2008 Page 630 of 1468 REJ09B0412-0200 13.2.7 Port B (1) PB7/SD φ The pin function is switched as shown below according to the combination of operating mode and the EXPE bit, the port function control register (PFCR), and the PB7DDR bit settings. Setting MCU Operating Mode I/O Port Module Name Pin Function SDRAM Mode PB7DDR Clock pulse generator SD φ output* 1 I/O port PB7 output 0 1 PB7 input (initial value) 0 0 Note: * Valid in SDRAM mode (2) PB6/ CS6-D/(RD/WR-B)/ADTRG0-B The pin function is switched as shown below according to the combination of operating mode and the EXPE bit, the bus controller register, the port function control register (PFCR), and the PB6DDR bit settings. Setting I/O Port Module Name Pin Function Byte control SRAM Selection (RD/ WR-B)_OE CS6D_OE PB6DDR 1 RD/ WR-B output* 0 1 Bus controller CS6-D output* 0 0 1 PB6 output 0 0 0 1 I/O port PB6 input (initial value) 0 0 0 0 Note: * Valid in external extended mode (EXPE = 1) |
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