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H8SX/1663R 数据表(PDF) 1281 Page - Renesas Technology Corp |
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H8SX/1663R 数据表(HTML) 1281 Page - Renesas Technology Corp |
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1281 / 1504 page ![]() Section 28 Power-Down Modes Rev. 2.00 Sep. 24, 2008 Page 1249 of 1468 REJ09B0412-0200 28.2.5 Deep Standby Wait Control Register (DPSWCR) DPSWCR selects the time for which the MCU waits until the clock settles when deep software standby mode is canceled by an interrupt. DPSWCR is not initialized by the internal reset signal upon exit from deep software standby mode. Bit Bit name Initial value: R/W: 7 0 R/W 6 0 R/W 5 WTSTS5 0 R/W 4 WTSTS4 0 R/W 3 WTSTS3 0 R/W 2 WTSTS2 0 R/W 1 WTSTS1 0 R/W 0 WTSTS0 0 R/W Bit Bit Name Initial Value R/W Module 7, 6 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. |
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