H8SXSLASH1663M datasheet(518/1504 Pages) RENESAS

518 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 486 of 1468

REJ09B0412-0200

Transfer

Total transfer

size (EDTCR)

Address T

Address B

Address TB

Address BB

Figure 11.8 Normal Transfer Mode Operation

(2)

Repeat Transfer Mode

In repeat transfer mode, transfer of one data access size unit is processed in response to one

transfer request. The total transfer size of up to 4 Gbytes can be set by EDTCR. The repeat size of

up to 64 kbytes

× data access size can be set by EDBSR.

The ARS1 and ARS0 bits in EDACR specify the repeat area on the source address or destination

address side. The address specified for the repeat area is restored to the transfer start address at the

end of a repeat-size transfer. This operation continues until transfer of total transfer size set in

EDTCR ends. EDTCR specified with H'00000000 is assumed as free-running mode and the repeat

transfer continues until the DTE bit in EDMDR is cleared to 0.

At the end of a repeat-size transfer, the EXDMA transfer is halted temporarily and a repeat size

end interrupt is requested to the CPU or DTC. When the RPTIE bit in EDACR is set to 1 and the

next transfer request is generated at the end of a repeat-size transfer, the ESIF bit in EDMDR is set

to 1 and the DTE bit in EDMDR is cleared to 0 to terminate the transfer. At this time, an interrupt

is requested to the CPU or DTC when the ESIE bit in EDMDR is set to 1.

The timing of EXDMA transfer including the

ETEND or EDRAK output is the same as for

normal transfer mode.

Figure 11.9 shows the repeat transfer mode operation in dual address mode.

The operation without specifying a repeat area on the source or destination address side is the

same as for the normal transfer mode operation shown in figure 11.8. In this case, a repeat size end

interrupt can also be generated at the end of a repeat-size transfer.

H8SX/1663M 数据表(PDF) 518 Page - Renesas Technology Corp