H8SXSLASH1663M datasheet(77/1504 Pages) RENESAS

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Section 2 CPU

Rev. 2.00 Sep. 24, 2008 Page 45 of 1468

REJ09B0412-0200

2.5.3

Condition-Code Register (CCR)

CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask

(I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C)

flags.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC

instructions. The N, Z, V, and C flags are used as branch conditions for conditional branch (Bcc)

instructions.

Bit

Bit Name

Initial

Value

R/W

Description

R/W

Interrupt Mask Bit

Masks interrupts when set to 1. This bit is set to 1 at

the start of an exception handling.

Undefined

R/W

User Bit

Can be written to and read from by software using the

LDC, STC, ANDC, ORC, and XORC instructions.

Undefined

R/W

Half-Carry Flag

When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,

or NEG.B instruction is executed, this flag is set to 1 if

there is a carry or borrow at bit 3, and cleared to 0

otherwise. When the ADD.W, SUB.W, CMP.W, or

NEG.W instruction is executed, this flag is set to 1 if

there is a carry or borrow at bit 11, and cleared to 0

otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L

instruction is executed, this flag is set to 1 if there is a

carry or borrow at bit 27, and cleared to 0 otherwise.

Undefined

R/W

User Bit

Can be written to and read from by software using the

LDC, STC, ANDC, ORC, and XORC instructions.

Undefined

R/W

Negative Flag

Stores the value of the most significant bit (regarded as

sign bit) of data.

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