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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX/1663M 数据表(PDF) 547 Page - Renesas Technology Corp |
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H8SX/1663M 数据表(HTML) 547 Page - Renesas Technology Corp |
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547 / 1504 page  Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Sep. 24, 2008 Page 515 of 1468 REJ09B0412-0200 11.5.11 Bus Cycles in Single Address Mode (1) Single Address Mode (Read in Cycle Steal Mode) In single address mode, the bus is released after one byte, word, or longword has been transferred in response to one transfer request. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. Figure 11.34 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. Bus released Bus release Bus release EXDMA read EXDMA read EXDMA read EXDMA read B φ Address bus Bus release Bus release Last transfer cycle RD ETEND EDACK Figure 11.34 Example of Single Address Mode (Byte Read) Transfer |
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