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数据搜索系统，热门电子元器件搜索 |
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H8SX/1663M 数据表(PDF) 608 Page - Renesas Technology Corp |
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H8SX/1663M 数据表(HTML) 608 Page - Renesas Technology Corp |
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608 / 1504 page  Section 12 Data Transfer Controller (DTC) Rev. 2.00 Sep. 24, 2008 Page 576 of 1468 REJ09B0412-0200 Table 12.3 Chain Transfer Conditions 1st Transfer 2nd Transfer CHNE CHNS DISEL Transfer Counter* 1 CHNE CHNS DISEL Transfer Counter* 1 DTC Transfer 0 0 Not 0 Ends at 1st transfer 0 0 0* 2 Ends at 1st transfer 0 1 Interrupt request to CPU 0 0 Not 0 Ends at 2nd transfer 0 0 0* 2 Ends at 2nd transfer 1 0 0 1 Interrupt request to CPU 1 1 0 Not 0 Ends at 1st transfer 0 0 Not 0 Ends at 2nd transfer 0 0 0* 2 Ends at 2nd transfer 1 1 0* 2 0 1 Interrupt request to CPU 1 1 1 Not 0 Ends at 1st transfer Interrupt request to CPU Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer mode 2. When the contents of the CRAH is written to the CRAL in repeat transfer mode 12.5.1 Bus Cycle Division When the transfer data size is word and the SAR and DAR values are not a multiple of 2, the bus cycle is divided and the transfer data is read from or written to in bytes. Table 12.4 shows the relationship among, SAR, DAR, transfer data size, bus cycle divisions, and access data size. Figure 12.5 shows the bus cycle division example. Table 12.4 Number of Bus Cycle Divisions and Access Size Specified Data Size SAR and DAR Values Byte (B) Word (W) Longword (LW) Address 4n 1 (B) 1 (W) 1 (LW) Address 2n + 1 1 (B) 2 (B-B) 3 (B-W-B) Address 4n + 2 1 (B) 1 (W) 2 (W-W) |
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