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H8SX/1663M 数据表(PDF) 773 Page - Renesas Technology Corp |
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H8SX/1663M 数据表(HTML) 773 Page - Renesas Technology Corp |
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773 / 1504 page  Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Sep. 24, 2008 Page 741 of 1468 REJ09B0412-0200 (b) When TGR is an input capture register Figure 14.17 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. TCNT value H'09FB H'0000 TGRC Time H'0532 TIOCA TGRA H'0F07 H'0532 H'0F07 H'0532 H'0F07 H'09FB Figure 14.17 Example of Buffer Operation (2) |
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