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H8SX/1663M 数据表(PDF) 1151 Page - Renesas Technology Corp |
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H8SX/1663M 数据表(HTML) 1151 Page - Renesas Technology Corp |
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1151 / 1504 page ![]() Section 25 Flash Memory Rev. 2.00 Sep. 24, 2008 Page 1119 of 1468 REJ09B0412-0200 Bit Bit Name Initial Value R/W Description 7 6 5 1 0 0 R R R Reserved These are read-only bits and cannot be modified. 4 FLER 0 R Flash Memory Error Indicates that an error has occurred during programming or erasing the flash memory. When this bit is set to 1, the flash memory enters the error protection state. When this bit is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to the flash memory, the reset must be released after the reset input period (period of RES = 0) of at least 100 µs. 0: Flash memory operates normally (Error protection is invalid) [Clearing condition] • At a reset 1: An error occurs during programming/erasing flash memory (Error protection is valid) [Setting conditions] • When an interrupt, such as NMI, occurs during programming/erasure. • When the flash memory is read during programming/erasure (including a vector read and an instruction fetch). • When the SLEEP instruction is executed during programming/erasure (including software standby mode). • When a bus master other than the CPU, such as the DMAC and DTC, obtains bus mastership during programming/erasure. |
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