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H8SX/1663M 数据表(PDF) 1287 Page - Renesas Technology Corp

部件名 H8SX/1663M
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663M 数据表(HTML) 1287 Page - Renesas Technology Corp

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Section 28 Power-Down Modes
Rev. 2.00 Sep. 24, 2008 Page 1255 of 1468
REJ09B0412-0200
28.2.8
Deep Standby Interrupt Edge Register (DPSIEGR)
DPSIEGR selects the rising or falling edge to clear deep software standby mode.
DPSIEGR is not initialized by the internal reset signal upon exit from deep software standby
mode.
Bit
Bit name
Initial value:
R/W:
7
DNMIEG
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
DIRQ3EG
0
R/W
2
DIRQ2EG
0
R/W
1
DIRQ1EG
0
R/W
0
DIRQ0EG
0
R/W
Bit
Bit Name
Initial
Value
R/W
Module
7
DNMIEG
0
R/W
NMI Edge Select
Selects the active edge for NMI pin input.
0: The interrupt request is generated by a falling edge.
1: The interrupt request is generated by a rising edge.
6 to 4
All 0
R/W
Reserved
These bits are always read as 0. The write value should
always be 0.
3
DIRQ3EG
0
R/W
IRQ3 Interrupt Edge Select
Selects the active edge for IRQ3-A pin input.
0: The interrupt request is generated by a falling edge.
1: The interrupt request is generated by a rising edge.
2
DIRQ2EG
0
R/W
IRQ2 Interrupt Edge Select
Selects the active edge for IRQ2-A pin input.
0: The interrupt request is generated by a falling edge.
1: The interrupt request is generated by a rising edge.
1
DIRQ1EG
0
R/W
IRQ1 Interrupt Edge Select
Selects the active edge for IRQ1-A pin input.
0: The interrupt request is generated by a falling edge.
1: The interrupt request is generated by a rising edge.



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