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H8SX/1663M 数据表(PDF) 1390 Page - Renesas Technology Corp |
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H8SX/1663M 数据表(HTML) 1390 Page - Renesas Technology Corp |
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1390 / 1504 page  Section 29 List of Registers Rev. 2.00 Sep. 24, 2008 Page 1358 of 1468 REJ09B0412-0200 Register Abbreviation Reset Module Stop State Sleep All-Module- Clock-Stop Software Standby Deep Software Standby Hardware Standby Module TGRC_3 Initialized Initialized* 1 Initialized TGRD_3 Initialized Initialized* 1 Initialized TPU_3 Notes: 1. Not initialized in deep software standby mode but initialized when deep software standby mode is released by the internal reset. 2. These registers are initialized when all the RAMCUT2 to RAMCUT0 bits in DPSBYCR are set to 1, and not initialized when these bits are set to 0. 3. Supported only by the H8SX/1668M Group. 4. LVDCR is initialized by a pin reset or power-on reset not by a voltage-monitoring reset, deep software standby reset, or watchdog timer reset. |
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