H8SXSLASH1663M datasheet(1494/1504 Pages) RENESAS

1494 / 1504 page

Rev. 2.00 Sep. 24, 2008 Page 1462 of 1468

REJ09B0412-0200

Cluster transfer modes ............................ 481

Cluster transfer read address mode......... 533

Cluster transfer write address mode ....... 535

Communications protocol..................... 1176

Compare match A................................... 834

Compare match B ................................... 835

Compare match count mode ................... 837

Compare match signal ............................ 834

Control transfer..................................... 1012

Counter operation ................................... 730

CPU priority control function over

DTC and DMAC .................................... 165

CRC operation circuit............................. 958

Crystal resonator................................... 1227

Cycle steal mode..................................... 491

Cycle stealing mode................................ 413

D/A converter ....................................... 1097

Data direction register ............................ 604

Data register............................................ 605

Data stage ............................................. 1014

Data transfer controller (DTC) ............... 559

Direct convention ................................... 937

DMA controller (DMAC)....................... 375

Double-buffered structure....................... 912

Download pass/fail result parameter..... 1127

DRAM interface ..................................... 280

DRAM Interface..................................... 234

DTC vector address ................................ 571

DTC vector address offset ...... 571, 572, 573

Dual address mode.......................... 402, 482

Endian and data alignment ..................... 241

Endian format ......................................... 232

Error protection .................................... 1168

Error signal ............................................. 937

Exception handling ................................. 113

Exception-handling state........................... 76

EXDMA controller (EXDMAC) ............ 453

Extended repeat area............................... 399

Extended repeat area function......... 415, 492

Extension of chip select (

CS) assertion

period ...................................................... 254

External access bus ................................. 220

External bus ............................................ 225

External bus clock (B

φ) ................ 221, 1221

External bus interface ............................. 231

External clock ....................................... 1228

External interrupts................................... 147

Flash erase block select parameter........ 1136

Flash memory ....................................... 1105

Flash multipurpose address area

parameter .............................................. 1134

Flash multipurpose data destination

parameter .............................................. 1135

Flash pass and fail parameter................ 1128

Flash program/erase frequency

parameter .................................... 1132, 1151

Free-running count operation.................. 731

Frequency divider ....................... 1221, 1229

Full address mode ................................... 569

Full-scale error...................................... 1090

General illegal instructions ..................... 126

Hardware protection ............................. 1167

Hardware standby mode ............. 1236, 1279

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