H8SXSLASH1663M datasheet(170/1504 Pages) RENESAS

170 / 1504 page

Section 7 Interrupt Controller

Rev. 2.00 Sep. 24, 2008 Page 138 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

IRQ7E

R/W

IRQ7 Enable

The IRQ7 interrupt request is enabled when this bit is 1.

IRQ6E

R/W

IRQ6 Enable

The IRQ6 interrupt request is enabled when this bit is 1.

IRQ5E

R/W

IRQ5 Enable

The IRQ5 interrupt request is enabled when this bit is 1.

IRQ4E

R/W

IRQ4 Enable

The IRQ4 interrupt request is enabled when this bit is 1.

IRQ3E

R/W

IRQ3 Enable

The IRQ3 interrupt request is enabled when this bit is 1.

IRQ2E

R/W

IRQ2 Enable

The IRQ2 interrupt request is enabled when this bit is 1.

IRQ1E

R/W

IRQ1 Enable

The IRQ1 interrupt request is enabled when this bit is 1.

IRQ0E

R/W

IRQ0 Enable

The IRQ0 interrupt request is enabled when this bit is 1.

Note:

Supported only by the H8SX/1668M Group.

7.3.5

IRQ Sense Control Registers H and L (ISCRH, ISCRL)

ISCRH and ISCRL select the source that generates an interrupt request from IRQ15, IRQ14, and

IRQ11 to IRQ0 input.

Upon changing the setting of ISCR, IRQnF (n = 0 to 11, 14, 15) in ISR is often set to 1

accidentally through an internal operation. In this case, an interrupt exception handling is executed

if an IRQn interrupt request is enabled. In order to prevent such an accidental interrupt from

occurring, the setting of ISCR should be changed while the IRQn interrupt is disabled, and then

the IRQnF in ISR should be cleared to 0.

H8SX/1663M 数据表(PDF) 170 Page - Renesas Technology Corp

H8SX/1663M 数据表(HTML) 170 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载