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H8SX/1663M 数据表(PDF) 194 Page - Renesas Technology Corp |
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H8SX/1663M 数据表(HTML) 194 Page - Renesas Technology Corp |
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194 / 1504 page  Section 7 Interrupt Controller Rev. 2.00 Sep. 24, 2008 Page 162 of 1468 REJ09B0412-0200 Table 7.5 Number of Execution States in Interrupt Handling Routine Object of Access External Device 8-Bit Bus 16-Bit Bus Symbol On-Chip Memory 2-State Access 3-State Access 2-State Access 3-State Access Vector fetch S h 1 8 12 + 4m 4 6 + 2m Instruction fetch S I 1 4 6 + 2m 2 3 + m Stack manipulation S K 1 8 12 + 4m 4 6 + 2m [Legend] m: Number of wait cycles in an external device access. 7.6.5 DTC and DMAC Activation by Interrupt The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to the CPU • Activation request to the DTC • Activation request to the DMAC • Combination of the above For details on interrupt requests that can be used to activate the DTC and DMAC, see table 7.2, section 10, DMA Controller (DMAC), and section 12, Data Transfer Controller (DTC). |
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