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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX/1663M 数据表(PDF) 203 Page - Renesas Technology Corp |
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H8SX/1663M 数据表(HTML) 203 Page - Renesas Technology Corp |
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203 / 1504 page  Section 8 User Break Controller (UBC) Rev. 2.00 Sep. 24, 2008 Page 171 of 1468 REJ09B0412-0200 Section 8 User Break Controller (UBC) The user break controller (UBC) generates a UBC break interrupt request each time the state of the program counter matches a specified break condition. The UBC break interrupt is a non- maskable interrupt and is always accepted, regardless of the interrupt control mode and the state of the interrupt mask bit of the CPU. For each channel, the break control register (BRCR) and break address register (BAR) are used to specify the break condition as a combination of address bits and type of bus cycle. Four break conditions are independently specifiable on four channels, A to D. 8.1 Features • Number of break channels: four (channels A, B, C, and D) • Break comparison conditions (each channel) Address Bus master (CPU cycle) Bus cycle (instruction execution (PC break)) • UBC break interrupt exception handling is executed immediately before execution of the instruction fetched from the specified address (PC break). • Module stop state can be set |
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