H8SLASH3024 datasheet(3/841 Pages) RENESAS

3 / 841 page

Rev. 2.00 Sep 20, 2005 page iii of xxxviii

Preface

The H8/3024 Group is a high-performance single-chip microcomputer that integrates peripheral

functions necessary for system configuration with an H8/300H CPU featuring a 32-bit internal

architecture as its core.

The on-chip peripheral functions include ROM, RAM, 16-bit timers, 8-bit timers, a programmable

timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI),

a D/A converter, an A/D converter, and I/O ports, providing an ideal configuration as a

microcomputer for embedding in sophisticated control systems. Flash memory (F-ZTAT™*) and

mask ROM are available as on-chip ROM, enabling users to respond quickly and flexibly to

changing application specifications and the demands of the transition from initial to full-fledged

volume production.

Note: * F-ZTAT is a trademark of Renesas Technology Corp.

Intended Readership: This manual is intended for users undertaking the design of an application

system using the H8/3024 Group. Readers using this manual require a basic

knowledge of electrical circuits, logic circuits, and microcomputers.

Purpose:

The purpose of this manual is to give users an understanding of the hardware

functions and electrical characteristics of the H8/3024 Group. Details of

execution instructions can be found in the H8/300H Series Programming

Manual, which should be read in conjunction with the present manual.

Using this Manual:

• For an overall understanding of the H8/3024 Group’s functions

Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system

control functions, peripheral functions, and electrical characteristics.

• For a detailed understanding of CPU functions

Refer to the separate publication H8/300H Series Programming Manual.

Note on bit notation: Bits are shown in high-to-low order from left to right.

• For a detailed understanding of a register when its name is known

The addresses, bits, and initial values of the registers are summarized in appendix B, Internal

I/O Registers.

Related Material:

The latest information is available at our Web Site. Please make sure that you

have the most up-to-date information available.

(http://www.renesas.com/eng/)

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