HD6433044F datasheet(7/905 Pages) RENESAS

7 / 905 page

Rev. 7.00 Sep 21, 2005 page vii of xxiv

Main Revisions for this Edition

Item

Page

Revision (See Manual for Details)

All



All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and

other Hitachi brand names changed to Renesas Technology Corp.

Designation for categories changed from “series” to “group”

Table amended

Bit 6: RIE

Description

Receive-data-full (RXI) and receive-error (ERI) interrupt requests

are disabled*

(Initial value)

Receive-data-full (RXI) and receive-error (ERI) interrupt requests

are enabled

13.2.6 Serial Control

Bit 6-Receive

Interrupt Enable

(RIE)

461

19.5.3 Programming

Flowchart and

Sample Program

Flowchart for

Programming One

Byte

Figure 19.9

Programming

Flowchart

606

Figure amended

Enable watchdog timer*2

Select program mode

(P bit = 1 in FLMCR)

Wait (x) µs

Clear P bit

Disable watchdog timer

Select program-verify mode

(PV bit = 1 in FLMCR)

Verify (read memory)*3

No good

Clear PV bit

End (1-byte data programmed)

Programming ends

Clear PV bit

Programming error

≥ N?

n + 1

Double the programming

time (x

× 2 → x)

→ n

Yes

Verify ends

Clear

bit

Clear erase block register

(clear bit of programmed block to 0)

Clear

bit

Clear erase block register

(clear bit of block to be

programmed to 0)

Notes: 1. Write the data to be programmed using a

byte transfer instruction.

2. Set the watchdog timer overflow interval

by setting CKS2 and CKS1 to 0 and

CKS0 to 1.

3. Read to verify data from the memory

using a byte transfer instruction.

4. tVS1: 4 µs

5 to 10

µs

6 (set N so that total programming

time does not exceed 1 ms)

5. Programming time x, which is determined

by the initial time

× 2n–1 (n = 1 to 6),

increases in proportion to n. Thus, set the

initial time to 15.8

µs or less to make total

programming time 1 ms or less.

Wait (tVS1) µs*4

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