M16CSLASH62M datasheet(51/615 Pages) RENESAS

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Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Bus Control

1-32

_____

________

Figure 1.9.4. Example of RD signal extended by RDY signal

BCLK

CSi

(i=0 to 3)

RDY

tsu(RDY - BCLK)

BCLK

CSi

(i=0 to 3)

RDY

tsu(RDY - BCLK)

In an instance of separate bus

In an instance of multiplexed bus

Accept timing of RDY signal

: Wait using RDY signal

: Wait using software

Accept timing of RDY signal

________

Note: The RDY signal cannot be received immediately prior to a software wait.

Table 1.9.5. Microcomputer status in wait state (Note)

Item

Status

Oscillation

___

_____

R/W signal, address bus, data bus, CS

________

Maintain status when RDY signal received

__________

ALE signal, HLDA, programmable I/O ports

Internal peripheral circuits

________

(5) The RDY signal

________

RDY is a signal that facilitates access to an external device that requires long access time. As shown in

________

Figure 1.9.4, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state. If

________

an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.9.5

shows the state of the microcomputer with the bus in the wait state, and Figure 1.9.4 shows an example

____

________

in which the RD signal is prolonged by the RDY signal.

________

The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the

________

chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to

________

all bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as

properly as in non-using.

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