7220 datasheet(13/303 Pages) RENESAS

13 / 303 page

7220 Group User’s Manual

vii

List of figures

Fig. 2.15.1 Timing diagram at reset .......................................................................................... 2-95

Fig. 2.15.2 Internal state immediately after reset (1) ............................................................. 2-96

Fig. 2.15.3 Internal state immediately after reset (2) ............................................................. 2-97

Fig. 2.15.4 Internal state immediately after reset (3) (only M37221M8/MA-XXXSP) ........ 2-98

Fig. 2.15.5 Voltage at poweron reset ....................................................................................... 2-99

Fig. 2.15.6 Example of reset circuit (1) .................................................................................... 2-99

Fig. 2.15.7 Example of reset circuit (2) .................................................................................... 2-99

Fig. 2.16.1 Clock generating circuit block diagram ............................................................... 2-100

Fig. 2.17.1 Clock oscillation circuit using a ceramic resonator ........................................... 2-101

Fig. 2.17.2 External clock input circuit example .................................................................... 2-101

Fig. 2.17.3 Clock oscillation circuit for CRT display ............................................................. 2-101

CHAPTER 3. ELECTRICAL CHARACTERISTICS

Fig. 3.1.1 Definition diagram of timing on multi-master I2C-BUS ............................................ 3-5

CHAPTER 4. M37220M3-XXXSP/FP

Fig. 4.2.1 Pin configuration (top view) (1) ................................................................................. 4-4

Fig. 4.2.2 Pin configuration (top view) (2) ................................................................................. 4-5

Fig. 4.4.1 Functional block diagram ............................................................................................ 4-8

Fig. 4.5.1 Access area ................................................................................................................ 4-10

Fig. 4.5.2 Memory assignment ................................................................................................... 4-11

Fig. 4.5.3 Memory map of SFR (special function register) (1) ............................................. 4-12

Fig. 4.5.4 Memory map of SFR (special function register) (2) ............................................. 4-13

Fig. 4.5.5 Interrupt request register 1 (address 00FC16) ........................................................ 4-16

Fig. 4.5.6 Interrupt control register 1 (address 00FE16) ......................................................... 4-16

Fig. 4.5.7 D-A converter block diagram .................................................................................... 4-17

Fig. 4.5.8 DA n conversion register (addresses 00DE16 and 00DF16) .................................. 4-18

Fig. 4.5.9 Port P3 output mode control register (address 00CD16) ...................................... 4-18

Fig. 4.5.10 CRT display circuit block diagram ......................................................................... 4-20

Fig. 4.5.11 Example of display character data storing form .................................................. 4-21

Fig. 4.5.12 Structure of CRT display RAM .............................................................................. 4-23

Fig. 4.5.13 Border selection register (addresses 00E516) ...................................................... 4-24

Fig. 4.5.14 Color register n (addresses 00E616 to 00E916) .................................................... 4-24

Fig. 4.5.15 CRT control register (address 00EA16) ................................................................. 4-25

Fig. 4.5.16 CRT port control register (address 00EC16) ......................................................... 4-25

Fig. 4.5.17 Internal state immediately after reset (1) ............................................................. 4-26

Fig. 4.5.18 Internal state immediately after reset (2) ............................................................. 4-27

CHAPTER 5. APPLICATION

Fig. 5.1.1 Connection example .................................................................................................... 5-2

Fig. 5.1.2 Display example ........................................................................................................... 5-2

Fig. 5.1.3 Flowchart of initialization processing routine ........................................................... 5-3

Fig. 5.1.4 Flowchart of VSYNC interrupt processing routine ....................................................... 5-4

Fig. 5.1.5 Flowchart of CRT interrupt processing routine ........................................................ 5-5

Fig. 5.1.6 Set of display character data ..................................................................................... 5-6

Fig. 5.1.7 Example of setup timing for line counter and display character data .................. 5-7

Fig. 5.1.8 Timing of interrupt processing when not setting multiple interrupts ..................... 5-9

Fig. 5.1.9 Timing when all interrupt request bits are “1” at the same sampling point ..... 5-10

7220 数据表(PDF) 13 Page - Renesas Technology Corp

7220 数据表(HTML) 13 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载