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H8/3004 数据表(PDF) 97 Page - Renesas Technology Corp |
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H8/3004 数据表(HTML) 97 Page - Renesas Technology Corp |
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97 / 497 page  Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF). Figure 5-3 Timing of Setting of IRQnF Interrupts IRQ0 to IRQ4 have vector numbers 12 to 16. These interrupts are detected regardless of whether the corresponding pin is set for input or output. When using a pin for external interrupt input, clear its DDR bit to 0 and do not use the pin for SCI input or output. 5.3.2 Internal Interrupts Twenty-one internal interrupts are requested from the on-chip supporting modules. • Each on-chip supporting module has status flags for indicating interrupt status, and enable bits for enabling or disabling interrupts. • Interrupt priority levels can be assigned in IPRA and IPRB. 5.3.3 Interrupt Vector Table Table 5-3 lists the interrupt sources, their vector addresses, and their default priority order. In the default priority order, smaller vector numbers have higher priority. The priority of interrupts other than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order shown in table 5-3. ø IRQn IRQnF input pin Note: n = 4 to 0 83 |
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