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CONNECTION WITH EXTERNAL DEVICES

3.4 Hold function

7721 Group User’s Manual

3–12

3.4 Hold function

When composing the external circuit which accesses the bus without using the central processing unit

(CPU), Hold function is used to generate a timing for transferring the right to use the bus from the CPU to

the external circuit.

_____

The microcomputer enters Hold state by input of “L” level to the HOLD pin and retains this state while the

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level of the HOLD pin is at “L.” Table 3.4.1 lists the microcomputer’s state in Hold state.

In Hold state, the oscillation of the oscillator does not stop. Accordingly, the internal peripheral devices can

operate. However, Watchdog timer stops operating.

Table 3.4.1 Microcomputer’s state in Hold state

Item

Oscillation

φCPU

Pins A0 to A7, A8/D8 to A15/D15, A16/D0 to A23/D7, R/W,

___

____

BHE, BLE

Pins ALE, ST1

Pin ST0

φ1

Pins P43 to P47, P5 to P10 (Note)

Watchdog timer

State

Operating

Stopped at “L”

Stopped at “H”

Floating

Output “L” level.

Outputs “H” level.

Outputs clock

φ1.

Retain the state when Hold request was accepted.

Stopped

Note: This applies when this functions as a programmable I/O port.

3.4.1 Operation description

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Judgment of the HOLD pin input level is performed at every falling edge of

φ1. When “L” level is detected

at judgment of the input level, bus request (Hold) becomes “1,” when “H” level is detected, bus request

(Hold) becomes “0.”

Bus request (Hold) is sampled within a period when the bus request sampling signal is “1” and bus request

is accepted when there is no bus request (DRAMC). (This is called “Acceptance of Hold request.”) For bus

request, refer to section “13.2.1 Bus access control circuit.”

When Hold request is accepted,

φCPU stops at “L” level at the next rising edge of φ and the ST0 pin’s level

becomes “H,” the ST1 pin’s level becomes “L.” When 1 cycle of

φ has passed after the levels of the ST0

____

and ST1 pins are changed, the R/W, BHE, BLE pins and the external bus enter the floating state.

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In Hold state, when the HOLD pin’s input level becomes “H,” the ST0 and ST1 pins’ levels are changed

at the next rising edge of

φ. When 1 cycle of φ has passed after the levels of the ST0 and ST1 pins are

changed, the microcomputer terminates Hold state.

Figures 3.4.1 to 3.4.3 show timing of acceptance of Hold request and termination of Hold state.

Note:

φ has the same polarity and the same frequency as clock φ1.

However,

φ stops by acceptance of Ready request, or executing the STP or WIT instruction. Accordingly,

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judgment of the input level of the HOLD pin is not performed during Ready state.

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