M38041F1HKP datasheet(105/387 Pages) RENESAS

105 / 387 page

1-87

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

HARDWARE

FUNCTIONAL DESCRIPTION

Table 16 Definition of each bit in status register

q Status Register

The status register shows the operating status of the flash

memory and whether erase operations and programs ended suc-

cessfully or in error. It can be read in the following ways:

(1) By reading an arbitrary address from the User ROM area after

writing the read status register command (7016)

(2) By reading an arbitrary address from the User ROM area in the

period from when the program starts or erase operation starts

to when the read array command (FF16) is input.

Also, the status register can be cleared by writing the clear status

After reset, the status register is set to “8016”.

Table 16 shows the status register. Each bit in this register is ex-

plained below.

•Sequencer status (SR7)

The sequencer status indicates the operating status of the flash

memory. This bit is set to “0” (busy) during write or erase operation

and is set to “1” when these operations ends.

After power-on, the sequencer status is set to “1” (ready).

•Erase status (SR5)

The erase status indicates the operating status of erase operation.

If an erase error occurs, it is set to “1”. When the erase status is

cleared, it is reset to “0”.

•Program status (SR4)

The program status indicates the operating status of write opera-

tion. When a write error occurs, it is set to “1”.

The program status is reset to “0” when it is cleared.

If “1” is written for any of the SR5 and SR4 bits, the read array,

program, and block erase commands are not accepted. Before ex-

ecuting these commands, execute the clear status register

command (5016) and clear the status register.

Also, if any commands are not correct, both SR5 and SR4 are set

to “1”.

Each bit of

SRD bits

SR7 (bit7)

SR6 (bit6)

SR5 (bit5)

SR4 (bit4)

SR3 (bit3)

SR2 (bit2)

SR1 (bit1)

SR0 (bit0)

Sequencer status

Reserved

Erase status

Program status

Reserved

Status name

“1”

Ready

Terminated in error

“0”

Busy

Terminated normally

Definition

M38041F1HKP 数据表(PDF) 105 Page - Renesas Technology Corp

M38041F1HKP 数据表(HTML) 105 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载