M38042F1HKP datasheet(27/387 Pages) RENESAS

27 / 387 page

1-9

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

HARDWARE

FUNCTIONAL DESCRIPTION

Table 3 Push and pop instructions of accumulator or processor status register

Accumulator

Processor status register

Push instruction to stack

PHA

PHP

Pop instruction from stack

PLA

PLP

Fig. 7 Register push and pop at interrupt generation and subroutine call

Note: Condition for acceptance of an interrupt

Interrupt enable flag is “1”

Execute JSR

On-going Routine

M (S)(PCH)

(S)

(S) – 1

M (S)(PCL)

Execute RTS

(PCL)M (S)

(S)

(S)– 1

(S)

(S) + 1

(S)

(S) + 1

(PCH)M (S)

Subroutine

POP return

address from stack

Push return address

on stack

M (S)(PS)

Execute RTI

(PS)M (S)

(S)

(S) – 1

(S)

(S) + 1

Interrupt

Service Routine

POP contents of

processor status

M (S)(PCH)

(S)

(S) – 1

M (S)(PCL)

(S)

(S) – 1

(PCL)M (S)

(S)

(S) + 1

(S)

(S) + 1

(PCH)M (S)

POP return

address

from stack

I Flag is set from “0” to “1”

Fetch the jump vector

Push return address

on stack

Push contents of processor

status register on stack

Interrupt request

(Note)

Interrupt disable flag is “0”

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