SDA, SCL I

Symbol

Parameter

Min.

Typ.

Max.

Unit

SCL clock frequency

0

400

kHz

Bus free time between a STOP and START condition

1.3

µs

Hold time (repeated) START condition. After this period, the first

clock pulse is generated

0.6

µs

LOW period of the SCL clock

1.3

µs

HIGH period of the SCL clock

0.6

µs

Set-up time for a repeated START condition

0.6

µs

Data hold time

0.300

µs

Data set-up time

100

ns

Rise time of both SDA and SCL signals

20

300

ns (*)

Fall time of both SDA and SCL signals

20

300

ns (*)

Set-up time for STOP condition

0.6

µs

(*) Must be guaranteed by the I

SDA

SCL

PS

Sr

P

D95AU314

P= STOP

S = START

Definition of timing on the I

TDA7309

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