TDA7340G datasheet(20/27 Pages) STMICROELECTRONICS

20 / 27 page

In application, the soft mute ON programmation

should be followed by programmation of DIRECT

MUTE ON (see later) in order to achieve a final

100dB attenuation.

Beside the I2C bus programmation, the Soft Mute

ON can be generated in a fast way by forcing a

LOW level at pin phone GND, controlled by the

µP through a transistor. This approach is recom-

mended for fast RDS AF switching.

The Soft Mute status can be detected via I2C

bus, reading the Transmitted Byte, bit SM (see

data sheet pag.11).

read bit SM = 1 soft mute status ON

read bit SM = 0 soft mute status OFF

DIRECT MUTE

bit D3 = 1 Direct mute ON

bit D3 = 0 Direct nute OFF

The direct mute bit forces an internal immediate

signal connection to ground.

It is located just before the Volume/Loudness

stage, and gives a typical 100dB attenuation.

SPEAKERS MUTE

An additional direct mute function is included in

the speakers attenuators stage.

The four output LF, RF, LR, RR can be separately

muted by setting the speaker attenuator byte to

the value 11111111 binary.

Typical attenuation level 100dB. This mute is use-

ful for fader and balance functions. It should not

be applied for system mute/unmute, because it

can generate noise due to the offset of previous

stages (bass / treble).

ZEROCROSSING MUTE

bit D2=1 D4=0 zero crossing mute ON

bit D2=0 D4=0 zero crossing mute OFF

The mute activation/deactivation is delayed until

the signal waveform crosses the DC zero level

(Vref level).

The detection works separately for the left and

the right channels (see Figg. 14, 15). Four differ-

ent windows threshold are software selectable by

two dedicated bits.

bit D6 bit D5

WINDOW

Vref DC +/-160mV

Vref DC +/-80mV

Vref DC +/-40mV

Vref DC +/-20mV

The zero crossing mute activation/deactivation

starts when the AC signal level falls inside the se-

lected window (internal comparator).

The ZEROCROSS Mute (and Pause) detector is

always active. It can be disabled, if the feature is

not used, by forcing the bit D4=1 Zero crossing

and Pause detector reset.

In this way the internal comparator logic is

stopped, eliminating its switching noise.

The zero cross mute status is detected reading

the Transmitted Byte bit ZM.

bit ZM = 1 zero cross mute status ON

bit ZM = 0 zero cross mute status OFF

PAUSE FUNCTION

On chip is implemented a pause detector block.

It uses the same 4 windows threshold selectable

for the zero crossing mute, bit D6,D5 byte MUTE

(see above). The detector can be put in OFF by

forcing bit D4=1, otherwise it is active.

The Pause detector info is available at PAUSE

pin. A capacitor must be connected between

PAUSE pin and Ground.

When the incoming signal is detected to be out-

side the selected window, the external capacitor

is discharged. When the signal is inside the win-

dow, the capacitor is integrating up (see Figg.16

and 17).

The pause status can be detected in two ways:

a)by reading directly the Pause pin level.

The ON/OFF voltage threshold is 3.0V typical.

Pause OFF = level low (< 3.0V)

Pause ON = level high ( ; 3.0V)

b)by reading via I

2C bustheTransmittedByte,bit P

P= 0 pause active.

P= 1 no pause detected.

The external capacitor value fixes the time con-

stant.

The pull up current is 25uV typical

With input signal

Vin = 1Vrm --; Vdc pin pause = 15mV

Vin = 0Vrms --; Vdc pin pause = 5.62V

For example choosing Cpause = 100nF the

charge up constant is about 22ms. Instead with

Cpause = 15nF the charge up constant is about

360us.

The Pause detection is useful in applications like

RDS, to perform noiseless tuning frequeny jumps

avoiding to mute the signal.

NO SYMMETRICAL BASS CUT RESPONSE

bit D7=0 No symmetrical

bit D7=1 Symmetrical

The Bass stage

has the option to generate an

unsymmetrical response, for cut mode settings

(bass level from -2db to - 14dB)

For example using a T-type band pass external

TDA7340G

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