OUTPUT TIMING

The RDS (1187.5Hz) output clock on RDCL line

is synchronized to the incoming data.

According to the internal PLL lock condition data

change can result on the falling or on the rising

clock edge. (see Fig. 1)

Whichever clock edge is used by the decoder

(rising or falling edge) the data will remain valid

for 416.7

µsec after the clock transition.

OSCILLATOR CONTROLS (FSEL, OSEL)

Three different crystal frequencies can be used.

The adaption of the internal clock divider to the

external crystal is achieved via the input pin

FSEL. See the following table for reference:

Crystal

FSEL (pin configuration)

4.332MHz

8.664MHz

17.328MHz

connected to GND or open

connected to Vs

external resistor of 100K to Vs

A special mode is introduced to reduce EMI. With

pin OSEL connected to GND the internal oscilla-

tor is switched off and an external sinusoidal fre-

quency could be applied on OSCIN. The peak to

peak voltage of this signal can be reduced down

to 60mV.

In this mode the frequency selection via FSEL is

still active.

Suggested values of C1 and C2 are shown in the

following table:

Crystal

C1

C2

4.332MHz

8.664MHz

17.328MHz

27pF

27pF

27pF

47pF

-

-

Figure 1. RDS timing diagram

CLOCK

LINE

DATA

LINE

TDA7479

4/7