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narrow filtered IF2 before demodulation. A switch controlled by IF counter mode (IFCM) is chosing the input sig-

nal for IF counter.

The grade of integration is adjustable by eight different measuring cycle times. The tolerance of the accepted

count value is adjustable, to reach an optimum compromise for search speed and precision of the evaluation.

1.7.8

The IF-Counter Mode

The IF counter works in 3 modes controlled by IFCM register.

1.7.9

Sampling Timer

A sampling timer generates the gate signal for the main counter. The basically sampling time are in FM mode

ate several sampling times.

1.7.10 Intermediate Frequency Main Counter

This counter is a 11 - 21-bit synchronous autoreload down counter. Five bits (CF) are programmable to have

the possibility for an adjust to the centre frequency of the IF-filter. The counter length is automatic adjusted to

the chosen sampling time and the counter mode (FM, AM-UPC, AM).

At the start the counter will be loaded with a defined value which is an equivalent to the divider value

If a correct frequency is applied to the IF counter frequency input at the end of the sampling time the main

counter is changing its state from 0h to 1FFFFFh.

This is detected by a control logic and an external search stop output is changing from LOW to HIGH. The fre-

quency range inside which a successful count result is adjustable by the EW bits.

FM mode

AM up conversion mode

AM mode

Counter result succeeded:

Counter result failed:

The IF counter is only started by inlock information from the PLL part. It is enabled by software (IFENA).

1.7.11 Adjustment of the Measurement Sequence Time

The precision of the measurements is adjustable by controlling the discrimination window. This is adjustable by

programming the control registers EW.

The measurement time per cycle is adjustable by setting the registers IFS.

1.7.12 Adjust of the Frequency Value

The center frequency of the discrimination window is adjustable by the control registers CF.