5/11

TDA7521

Figure 2. TDA7521 timings in 768

×Fs mode

Fig.3.

× F

rising edge, while RF data change on the falling edge); (3.A, 3.B, 3.C, 3.D) Internally generated

96

× F

data OUT; (8) AC/RF/BD/RF/E/RF/F/RF data stream before digital MUX; (9) Output

AC/RF/BD/RF/E/RF/F/RF; (10) Synthesized clock; (11) Generic Bitstream Input; (12.A, 12.B,

× F

(1

(2

BD

AC

E

F

AC

BD

E

F

BD

E

F

AC

BD

E

F

RF

RF

RF

RF

RF

RF

RF

RF

RF

RF

RF

RF

RF

RF

RF

RF

RB

R

E

R

F

RARB

R

E

R

F

R

ARB

R

E

R

F

R

ARB

R

E

R

F

R

(4

(5

(6

(7

(8

(9

(3.B)

(3.A)

(3.C)

(3.D)

(10)

(11)

(12.A)

(12.B)

(12.C)