Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Output Voltage

5

5.1

5.2

V

Output Voltage

7.84

8

8.16

V

Output Voltage

4.9

5.3

V

Output Voltage

7.7

8.3

V

Dropout Voltage

1.4

V

Line Regulation

50

80

mV

mV

Load Regulation

100

160

mV

mV

Quiescent Current

Output 2 Disabled

2mA

Reset Thrseshold Voltage

K - 0.4

K -

0.25

K - 0.1

V

Reset Thrseshold Hysteresis

See circuit description

20

50

75

mV

Reset Pulse Delay

See circuit description

25

ms

Saturation Voltage in Reset Condition

0.4

V

Leakage Current in Normal Condition at Pin 6

10

µA

Output Voltage Thermal Drift

=

100

ppm/

Short Circuit Output Current

1.6

1

A

A

Disable Voltage High (out 2 active)

2

V

Disable Voltage Low (out 2 disabled)

0.8

V

Disable Bias Current

-100

2

µA

Junction Temperature for Thermal Shut Down

145

Note : Safe permanent short-circuit is only guaranteed for input voltages up to 16V.

The TDA8133 is a dual voltage regulator with Reset

and Disable.

The two regulation parts are supplied from one

voltage reference circuit trimmed by zener zap

during EWS test.

Since the supply voltage of this last is connected at

not supplied.

The outputs stage have been realized in darlington

configuration with a drop typical 1.2V.

The disable circuit, switch-off the output 2 if a

voltage lower than 0.8V is applied at Pin 4.

The Reset circuit checks the voltage at the out-

typ.), the comparator "a" (see Figure 1) discharges

at once Low. When the voltage at the out1 rises

increases linearly to 2.5V corresponding to a delay

=

⋅ 2.5V

10

(see Figure 2),

then the reset output goes high again. To avoid

gliches in the reset output, the second comparator

"b" has a large hysteresis (1.9V).

CIRCUIT DESCRIPTION

TDA8133

3/5