TDA9103 datasheet(13/27 Pages) STMICROELECTRONICS

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SMPS Output

Inhibition

VCC 30

REF 30

XRAY 30

VCCoff 30

H-duty Cycle 30

1V 30

Flyback 30

0.7V 30

PLL-Unloocked

VCC Checking

XRAY Protection

Inhibition

H Output

Inhibition

V Output

Inhibition

Blanking

Figure 11 : Safety Functions Block Diagram

20k

Ω

220nF

From

Phase

Comparator

NOR1

6.5V

NOR2

23 SBLK OUT

H-Lock CAP

Figure 12 : LOCK/UNLOCK Block Diagram

The TDA9103 also includes a LOCK/UNLOCK

identification block which sense in real-time

wheather the PLL is locked on the incomming

horizontal sync signal or not. The resulting informa-

tion is available on safety blanking output (Pin 23)

where it is mixed with others information (see Fig-

ure 11). The block diagram of the LOCK/UNLOCK

function is described in Figure 12.

The NOR1 gate is receiving the phase comparator

output pulses (which also drives the charge pump).

When the PLL is locked, on point A there is a very

small negative pulse (100ns) at each horizontal

cycle, so after R-C filter, there is a high level on Pin

13 which force SBLK to high level (provided other

inputs on NOR2 are also at low level).

When the PLL is unlocked, the 100ns negative

pulse on A becomesmuch larger and consequently

the average level on Pin 13 will decrease. When it

reaches 6.5V, point B goes to high level forcing

NOR2 open collector output to ”0”.

The status of Pin 13 is approximately the following :

- Near 0V when there is no H-SYNC,

- Between 0 and 4V with H-SYNC frequency differ-

H Osc

Sawtooth

Phase REF1

H Synchro

1.6V

6.4V

2.4V<Vb<4V

0.75T

0.25T

Phase REF1 is obtained by comparison between the sawtooth

and a DC voltage adjustable between 2.4V and 4V. The PLL1

ensures the exact coincidence between the signals phase REF

and HSYNS. A

± 45° phase adjustment is possible.

Figure 13 : PLL1 Timing Diagram

ent from VCO,

- Between 4 and 8V when H-SYNC frequency

= VCO frequency but not in phase,

- Near to 8V when PLL is locked.

It is important to notice that Pin 13 is not an output

pin and must only be used for filtering purpose (see

Figure 12).

TDA9103

13/27

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