BLK

HSYNC

BPCP

Figure 1

HSYNC

BPCP

Figure 2

FUNCTIONAL DESCRIPTION

Input Stage

The R, G and B signals must be fed to the three

inputs through coupling capacitors (100nF).

The maximum input peak-to-peak video amplitude

is 1V.

The input stage includes a clamping function. This

clamp is using the input serial capacitor as ”mem-

ory capacitor” and is gated by an internally gener-

ated ”Back-Porch-Clamping-Pulse (BPCP)”.

The synchronization edge of the BPCP is selected

according bit 0 of register R8.

When B0R8 is set to 1, the BPCP is synchronized

on the leading edge of the blanking pulse BLK

inputs on Pin 14 (see Figure 1).

When B0R8 is clear to 0, the BPCP is synchronized

on the second edge of the horizontal pulse HSYNC

inputs on Pin 24. An automatic function allows to

use positive or negative horizontal pulse on Pin 24

(see Figure 2).

In both case BPCP width is adjustable by I

and B2 of register R8 (see R8 Table P8).

Contrast Adjustment (8 bits)

The contrast adjustment is made by controlling

simultaneously the gain of three internal variable

gain amplifiers through the I

The contrast adjustment allows to cover a typical

range of 48dB.

Brightness Adjustment (8 bits)

As for the contrast adjustment, the brightness is

controlled by I

The brightness function consists to add the same

DC offset to the three R, G, B signals after contrast

amplification.

This DC-Offset is present only outside the blanking

pulse (see Figure 3).

The DC output level during the blanking pulse, is

Drive Adjustment (3 x 8 bits)

In order to adjust the white balance , the TDA9206

offers the possibility to adjust separately the overall

gain of each complete video channel.

The gain of each channel is controlled by I

each).

The very large drive adjustment range (48dB) allows

different standard or custom color temperature.

It can also be used to adjust the output voltages at

the optimum amplitude to drive the C.R.T drivers,

keeping the whole contrast control for end-user only.

The drive adjustment is located after the CON-

TRAST, BRIGHTNESS and OSD switch blocks, so

that the white balance will remains correct when

BRT is adjusted, and will also be correct on OSD

portion of the signal.

OSD Inputs

The TDA9206 includes all the circuitry necessary

to mix OSD signals into the RGB main-picture. Four

pins are dedicated to this function as follow.

Three TTL RGB On Screen Display inputs

(Pin 2, 5 and 8). These three inputs are connected

to the three outputs of the corresponding ON-

SCREEN-DISPLAY processor (ex : STV942x).

One Fast Blanking Input (FBLK, Pin 13) which is

also connected to the FBLK output of the same

ON-SCREEN-DISPLAY processor.

When a high level is present on FBLK, the IC will

acts as follow :

- The three main picture RGB input signals are

internally switched to the internal input clamp

reference voltage.

- The

three output signals are set to voltages

corresponding to the state (0 or 1) on the three

OSD inputs (see Figure 3).

Example :

If FBLK = 1 and OSD1, OSD2, OSD3) = 1, 0, 1

respectively.

BRT is the brightness DC level I

OSD is the On-Screen Display signal value I

Semi-transparent function is controlled thanks to

Bit 6 of R8 register (see Table 1).

When semi-transparent mode is activated, video

signal is divided by 2 (CONT).

TDA9206

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