TDA9210

3/19

3 - BLOCK DIAGRAM

4 - FUNCTIONAL DESCRIPTION

4.1 - RGB Input

The three RGB inputs have to be supplied through

coupling capacitors (100 nF).

The maximum input peak-to-peak video amplitude

is 1 V.

The input stage includes a clamping function. The

clamp uses the input serial capacitor as a ”memo-

ry capacitor”.

To avoid a discharge of the serial capacitor during

the line (due to leakage current), the input voltage

is referenced to the ground.

The clamp is gated by an internally generated

”Back Porch Clamping Pulse” (BPCP). Register 8

allows to choose the way to generate this BPCP

(see Figure 1).

When bit 0 is set to 0, the BPCP is synchronized

on the trailing or leading edge of HSYNC (Pin 19)

(bit 1 = 0: trailing edge, bit 1 = 1: leading edge).

BLK

FBLK

VCCP

OUT1

GNDP

OUT2

OUT3

IN1

IN2

IN3

ABL

GNDL

GNDA

VCCA

HSYNC

SDA SCL

OSD1

OSD2

OSD3

or BPCP

TDA9210

17

11

20

1

3

5

2

4

6

7

19

13

12

8

9

10

14

16

15

18

Output Clamp Pulse

(OCL)

Output

Stage

Drive

Contrast

Clamp

Green Channel

Blue Channel

Contrast/8bit

Latches

Bus

Decoder

D/A

BPCP

OSD

Cont.

4bits

Drive

3x8bits

Brightness

8bits

Output

DC Level

4bits

I C

Cut-off

8bits

See Figure 8 for complete BPCP and OCL generation diagram