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TS4851 数据表(PDF) 7 Page - STMicroelectronics |
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TS4851 数据表(HTML) 7 Page - STMicroelectronics |
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7 / 28 page ![]() Electrical Characteristics TS4851 7/28 4 Electrical Characteristics Table 8. Electrical characteristics at VCC = +5V, GND = 0V, Tamb = 25°C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit ICC Supply Current Output Mode 7, Vin = 0V, no load All other output modes, Vin = 0V, no load 8 4.5 11 6.5 mA ISTANDBY Standby Current Output Mode 0 0.1 2 µA Voo Output Offset Voltage (differential) Vin = 0V 5 50 mV Vil “Logic low” input Voltage 0 0.4 V Vih “Logic high” input Voltage 1.4 5 V Po Output Power SPKERout, RL = 8 Ω, THD = 1%, F = 1kHz Rout & Lout, RL = 32 Ω, THD = 0.5%, F = 1kHz 800 80 1000 120 mW THD + N Total Harmonic Distortion + Noise Rout & Lout, Po = 80mW, F = 1kHz, RL = 32 Ω SPKERout, Po = 800mW, F = 1kHz, RL = 8 Ω Rout & Lout, Po = 50mW, 20Hz < F < 20kHz, RL = 32 Ω SPKERout, Po = 40mW, 20Hz < F < 20kHz, RL = 8 Ω 0.5 1 0.5 1 % SNR Signal To Noise Ratio (A-Weighted) 90 dB PSRR Power Supply Rejection Ratio1 Vripple = 200mV Vpp, F = 217Hz, Input(s) Terminated 10 Ω Ouput Mode 1 Ouput Mode 2 Ouput Mode 3 (G=+12dB) Ouput Mode 4 (G=+12dB) Ouput Mode 5 (G=+12dB) Ouput Mode 6, 7 (G=+12dB) 1) Dynamic measurements [20 x log(rms(Vout)/rms(Vripple)]. Vripple is the superimposed sinus signal to Vcc @ F = 217Hz 70 70 55 57 52 56 dB G Digital Gain Range - Rin & Lin no load -34.5 +12 dB Digital gain stepsize 1.5 dB Stepsize G ≥ -22.5dB G < -22.5dB -0.5 -1 +0.5 +1 dB Phone In Gain, no load BTL gain from Phone In to SPKERout BTL gain from Phone In to Rout & Lout 6 0 dB Zin Phone In Input Impedance 15 20 25 k Ω Zin Rin & Lin Input Impedance (all gain setting) 37.5 50 62.5 k Ω tes Enable Stepup Time - ENB 20 ns teh Enable Hold Time - ENB 20 ns tel Enable Low Time - ENB 30 ns tds Data Setup Time- DATA 20 ns tdh Data Hold Time - DATA 20 ns tcs Clock Setup time - CLK 20 ns tch Clock Logic High Time - CLK 50 ns tcl Clock Logic Low Time - CLK 50 ns fclk Clock Frequency - CLK DC 10 MHz |
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