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ADA4927-2YCPZ-R2 数据表(PDF) 22 Page - Analog Devices |
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ADA4927-2YCPZ-R2 数据表(HTML) 22 Page - Analog Devices |
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22 / 24 page ![]() ADA4927-1/ADA4927-2 Rev. 0 | Page 22 of 24 LAYOUT, GROUNDING, AND BYPASSING As a high speed device, the ADA4927 is sensitive to the PCB environment in which it operates. Realizing its superior performance requires attention to the details of high speed PCB design. This section shows a detailed example of how the ADA4927-1 was addressed. The first requirement is a solid ground plane that covers as much of the board area around the ADA4927-1 as possible. However, clear the area near the feedback resistors (RF), gain resistors (RG), and the input summing nodes (Pin 2 and Pin 3) of all ground and power planes (see Figure 55). Clearing the ground and power planes minimizes any stray capacitance at these nodes and prevents peaking of the response of the amplifier at high frequencies. Whereas ideal current feedback amplifiers are insensitive to summing node capacitance, real-world amplifiers can exhibit peaking due to excessive summing node capacitance. The thermal resistance, θJA, is specified for the device, including the exposed pad, soldered to a high thermal conductivity 4-layer circuit board, as described in EIA/JESD 51-7. Figure 55. Ground and Power Plane Voiding in Vicinity of RF AND RG Bypassed the power supply pins as close to the device as possible and directly to a nearby ground plane. Use high frequency ceramic chip capacitors. It is recommended that two parallel bypass capacitors (1000 pF and 0.1 μF) be used for each supply. The 1000 pF capacitor should be placed closer to the device. Further away, provide low frequency bulk bypassing, using 10 μF tantalum capacitors from each supply to ground. Make signal routing short and direct to avoid parasitic effects. Wherever complementary signals exist, provide a symmetrical layout to maximize balanced performance. When routing differential signals over a long distance, place PCB traces close together, and twist any differential wiring such that the loop area is minimized. Doing this reduces radiated energy and makes the circuit less susceptible to interference. 1.30 0.80 0.80 1.30 Figure 56. Recommended PCB Thermal Attach Pad Dimensions (Millimeters) 0.30 PLATED VIA HOLE 1.30 GROUND PLANE POWER PLANE BOTTOM METAL TOP METAL Figure 57. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters) |
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