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ADE5166/ADE5169

Rev. 0 | Page 16 of 148

Pin No.

Mnemonic

Description

P0.3/CF2

General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives

instantaneous active, reactive, Irms, or apparent power information.

P0.2/CF1/RTCCAL

General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1/RTC Calibration Frequency Logic

Output. The CF1 logic output gives instantaneous active, reactive, or apparent power or Irms, information. The

RTCCAL logic output gives access to the calibrated RTC output.

SDEN/P2.3/TxD2

Serial Download Mode Enable/General-Purpose Digital Output Port P2.3/Transmitter Data Output 2

(Asynchronous). This pin is used to enable serial download mode through a resistor when pulled low on

power-up or reset. On reset, this pin momentarily becomes an input, and the status of the pin is sampled. If

there is no pull-down resistor in place, the pin momentarily goes high and then user code is executed. If the

pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains

low during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3)

or as Transmitter Data Output 2 (asynchronous).

BCTRL/INT1/P0.0

Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic

input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left

open, the connection between VDD or VBAT and VSWOUT is selected internally.

XTAL2

A crystal can be connected across this pin and XTAL1 (see XTAL1 pin description) to provide a clock source

for the ADE5166/ADE5169. The XTAL2 pin can drive one CMOS load when an external clock is supplied at

XTAL1 or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin.

XTAL1

An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected

across XTAL1 and XTAL2 to provide a clock source for the ADE5166/ADE5169. The clock frequency for

specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin.

INT0

External Interrupt Input 0.

49, 50

VP, VN

Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum

differential level of ±400 mV for specified operation. This channel also has an internal PGA.

This pin is used as an input for emulation. When held high, this input enables the device to fetch code from

internal program memory locations. The ADE5169 does not support external code memory. This pin should

not be left floating.

52, 53

IPA, IN

Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum

differential level of ±400 mV for specified operation. This channel also has an internal PGA.

AGND

This pin provides the ground reference for the analog circuitry.

IPB

Analog Input for Second Current Channel. This input is fully differential with a maximum differential level of

±400 mV, referred to IN for specified operation. This channel also has an internal PGA.

RESET

Reset Input, Active Low.

REFIN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

1.2 V ± 0.1% and a typical temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled

with a 1 μF capacitor in parallel with a ceramic 100 nF capacitor.

VBAT

Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to VDD when

the battery is selected as the power supply for the ADE5166/ADE5169.

VINTA

This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to

this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

VDD

3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is

selected as the power supply for the ADE5166/ADE5169. This pin should be decoupled with a 10 μF

capacitor in parallel with a ceramic 100 nF capacitor.

VSWOUT

3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the

ADE5166/ADE5169. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF

capacitor.

VINTD

This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to

this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

DGND

This pin provides the ground reference for the digital circuitry.

VDCIN

Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to

AGND. This pin is used to monitor the preregulated dc voltage.

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