ADE5166ASTZF62 datasheet(57/148 Pages) AD

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ADE5166/ADE5169

Rev. 0 | Page 57 of 148

POS

INTERRUPT STATUS REGISTERS

NEG

APSIGN FLAG

NO LOAD

THRESHOLD

ACTIVE POWER

NO LOAD

THRESHOLD

ACTIVE ENERGY

Line Cycle Active Energy Accumulation Mode

In line cycle active energy accumulation mode, the energy accumu-

lation of the ADE5166/ADE5169 can be synchronized to the

voltage channel zero crossing so that active energy can be

accumulated over an integral number of half-line cycles. The

advantage of summing the active energy over an integer number

of line cycles is that the sinusoidal component in the active energy

is reduced to 0. This eliminates any ripple in the energy calculation.

Energy is calculated more accurately and more quickly because

the integration period can be shortened. By using this mode,

the energy calibration can be greatly simplified, and the time

required to calibrate the meter can be significantly reduced.

In the line cycle active energy accumulation mode, the ADE5166/

ADE5169 accumulate the active power signal in the LWATTHR

shown in Figure 65. The number of half-line cycles is specified in

the LINCYC register (Address 0x12).

APNOLOAD

The ADE5166/ADE5169 can accumulate active power for up to

65,535 half-line cycles. Because the active power is integrated

on an integral number of line cycles, the CYCEND flag (Bit 2) in

the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) is set at the

end of an active energy accumulation line cycle. If the CYCEND

enable bit (Bit 2) in the Interrupt Enable 3 SFR (MIRQENH,

Address 0xDB) is set, the 8052 core has a pending ADE interrupt.

The ADE interrupt stays active until the CYCEND status bit is

cleared (see the Energy Measurement Interrupts section). Another

calibration cycle starts as soon as the CYCEND flag is set. If the

LWATTHR register (Address 0x03) is not read before a new

CYCEND flag is set, the LWATTHR register is overwritten by

a new value.

Figure 64. Energy Accumulation in Absolute Accumulation Mode

Active Energy Pulse Output

All of the ADE5166/ADE5169 circuitry has a pulse output whose

frequency is proportional to active power (see the Active Power

Calculation section). This pulse frequency output uses the

calibrated signal from the WGAIN register (Address 0x1D)

output, and its behavior is consistent with the setting of the

active energy accumulation mode in the ACCMODE register

(Address 0x0F). The pulse output is active low and should

preferably be connected to an LED, as shown in Figure 75.

DIGITAL-TO-FREQUENCY

CONVERTER

WDIV[7:0]

WATTOS[15:0]

WGAIN[11:0]

LPF1

LWATTHR[23:0]

ACCUMULATE

ACTIVE ENERGY IN

INTERNAL REGISTER

AND UPDATE THE

LWATTHR REGISTER

AT THE END OF LINCYC

HALF-LINE CYCLES

OUTPUT

FROM

LPF2

FROM VOLTAGE

CHANNEL

ADC

LINCYC[15:0]

ZERO-CROSSING

DETECTION

CALIBRATION

CONTROL

Figure 65. Line Cycle Active Energy Accumulation

ADE5166ASTZF62 数据表(PDF) 57 Page - Analog Devices

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