TS5071N datasheet(18/32 Pages) STMICROELECTRONICS

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TIMING SPECIFICATIONS

Unless otherwisenoted,limits in BOLD charactersare

guaranteed for VCC =+ 5 V

± 5%; VSS = -5V ± 5%.

TA = -40

°Cto 85 °C by correlation with 100 % elec-

trical testing at TA =25

°C. All other limits are as-

sured by correlation with other production tests

and/or product design and characterization. All sig-

nals referenced to GND. Typicals specified at

VCC =+ 5 V, VSS =-5 V, TA =25

°C. All timing pa-

rametersaremeasuredat VOH =2.0V andVOL =0.7 V.

See Definitions and Timing Conventions section

for test methods information.

ELECTRICAL OPERATING CHARACTERISTICS (continued)

POWER DISSIPATION

Symbol

Parameter

Min.

Typ.

Max.

Unit

ICC0

Power Down Current (CCLK, CI/O, CI = 0.4V, CS = 2.4V)

Interface Latches set as Outputs with no load

All over Inputs active, Power Amp Disabled

0.3

1.5

-ISS0

Power Down Current (as above)

0.1

0.3

ICC1

Power Up Current (CCLK, CI/O, CI = 0.4V, CS = 2.4V)

No Load on Power Amp

Interface Latches set as Outputs with no Load

-ISS1

Power Up Current (as above)

ICC2

Power Down Current with Power Amp Enabled

-ISS2

Power Down Current with Power Amp Enabled

MASTER CLOCK TIMING

Symbol

Parameter

Min.

Typ.

Max.

Unit

fMCLK

Frequency of MCLK

(selection of frequency is programmable, see table 2)

512

1.536

1.544

2.048

4.096

kHz

MHz

tWMH

Period of MCLK High (measured from VIH to VIH, see note 1)

tWML

Period of MCLK Low (measured from VIL to VIL, see note 1 )

tRM

Rise Time of MCLK (measured from VIL or VIH)30

tFM

Fall Time of MCLK (measured from VIH to VIL)30

tHBM

Hold Time, BCLK Low to MCLK High (TS5070 only)

tWFL

Period of FSX or FSR Low (Measured from VIL to VIL)

(*)

(*) MCLK period

TS5070 - TS5071

18/32

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