TSA0801 datasheet(15/20 Pages) STMICROELECTRONICS

15 / 20 page

TSA0801

15/20

Data Ready (DR)

The Data Ready output is an image of the clock

being synchronized on the output data (D0 to D9).

This is a very helpful signal that simplifies the syn-

chronization of the measurement equipment or

the controlling DSP.

As digital output, DR goes in high impedance state

when OEB is asserted to High level as described

in the timing diagram.

DRIVING THE ANALOG INPUT

Differential inputs

The TSA0801 has been designed to obtain opti-

mum performances when being differentially driv-

en. An RF transformer is a good way to achieve

such performances.

Figure 5 describes the schematics. The input sig-

nal is fed to the primary of the transformer, while

the secondary drives both ADC inputs. The com-

mon mode voltage of the ADC (INCM) is connect-

ed to the center-tap of the secondary of the trans-

former in order to bias the input signal around this

common voltage, internally set to 0.56V. The

INCM is decoupled to maintain a low noise level

on this node. Our evaluation board is mounted

with a 1:1 ADT1-1 transformer from Minicircuits.

You might also use a higher impedance ratio (1:2

or 1:4) to reduce the driving requirement on the

analog signal source.

Each analog input can drive a 1Vpp amplitude in-

put signal, so the resultant differential amplitude is

2Vpp.

Figure 5 : Differential input configuration

Single-ended input configuration

Some applications may require a single-ended

input

which

easily

achieved

with

the

configuration reported on Figure 6.

In this case, it is recommended to use an

AC-coupled analog input and connect the other

analog input to the common mode voltage of the

circuit (INCM) so as to properly bias the ADC. The

INCM may remain at the same internal level

(0.56V) thus supporting only a 1Vpp of input

amplitude, or it must be increased to 0.9V to

support a 2Vpp input amplitude. Performances

are better when using a 2Vpp signal.

Figure 6 : Single-ended input configuration

REFERENCE CONNECTION

Internal reference

In the standard configuration, the ADC is biased

with the internal reference voltage. VREFM pin is

connected to Analog Ground while VREFP is in-

ternally set to a voltage of 1.03V. It is recommend-

ed to decouple the VREFP in order to minimize

low and high frequency noise. Refer to Figure 7 for

the schematics.

Figure 7 : Internal reference setting

External reference

It is possible to use an external reference voltage

instead of the internal one for specific applications

requiring

even

better

linearity or

enhanced

tem0801perature behavior. In this case, the

amplitude of the external voltage must be at least

equal to the internal one (1.03V). Using the

STMicroelectronics Vref TS821 leads to optimum

TSA0801

VIN

VINB

INCM

Ω

100pF

330pF

470nF

10nF

Analog source

1:1

ADT1-1

TSA0801

VIN

VINB

INCM

Ω

100nF

330pF

470nF

10nF

Signal source

0.9V

TSA0801

VIN

VINB

VREFM

1.03V

VREFP

330pF

470nF

10nF

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