TSA1005

4/22

ELECTRICAL CHARACTERISTICS

AVCC = DVCC = VCCB = 2.5 V, Fs = 20/40 Msps, Fin = 10.13 MHz, Vin@ -1 dBFS, VREFP = 0.8 V,

VREFM = 0 V

Tamb = 25°C (unless otherwise specified)

TIMING CHARACTERISTICS

TIMING DIAGRAM

Symbol

Parameter.

1 Preliminary data.

TSA1005-40

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

FS

Sampling Frequency

0.5

20

0.5

40

MHz

DC

Clock Duty Cycle

50

45

50

55

%

TC1

Clock pulse width (high)

25

12.5

ns

TC2

Clock pulse width (low)

25

12.5

ns

Tod

Data Output Delay (Clock edge to Data

Valid) - 10pF load capacitance

55

ns

Tpd I

Data Pipeline delay for I channel

7

7

cycles

Tpd Q

Data Pipeline delay for Q channel

7.5

7.5

cycles

Ton

Falling edge of OEB to digital output

valid data

11

ns

Toff

Rising edge of OEB to digital output

tri-state

11

ns

N-1

N

N+1

N+6

N+7

N+2

N+5

N+3

N+4

N+8

CLK

Tpd I + Tod

N+9

N+10

N+11

N+12

N+13

DATA

OUTPUT

sample N+1

I channel

sample N

Q channel

sample N+1

Q channel

sample N+2

I channel

sample N+2

Q channel

sample N+3

I channel

OEB

Simultaneous sampling

on I/Q channels

SELECT

sample N-9

I channel

sample N-8

I channel

sample N-7

Q channel

sample N-6

Q channel

CLOCK AND SELECT CONNECTED TOGETHER

Tod

I

Q