MPC8313ECVRGDFA datasheet(13/100 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

RESET Initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and

electrical requirements of the MPC8313E.

5.1

RESET DC Electrical Characteristics

Table 9 provides the DC electrical characteristics for the RESET pins.

5.2

RESET AC Electrical Characteristics

Table 10 provides the reset initialization AC timing specifications.

Table 9. RESET Pins DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Input high voltage

VIH

—2.1

NVDD +0.3

Input low voltage

VIL

—

–0.3

0.8

Input current

IIN

0 V

≤ VIN ≤ NVDD

—±5

μA

Output high voltage

VOH

IOH = –8.0 mA

2.4

—

Output low voltage

VOL

IOL = 8.0 mA

—

0.5

Output low voltage

VOL

IOL = 3.2 mA

—

0.4

Table 10. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET or SRESET (input) to activate reset flow

—

tPCI_SYNC_IN

Required assertion time of PORESET with stable clock and power applied to

SYS_CLK_IN when the device is in PCI host mode

—

tSYS_CLK_IN

Required assertion time of PORESET with stable clock and power applied to

PCI_SYNC_IN when the device is in PCI agent mode

—

tPCI_SYNC_IN

HRESET assertion (output)

512

—

tPCI_SYNC_IN

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]

and CFG_SYS_CLK_IN_DIV) with respect to negation of PORESET when

the device is in PCI host mode

4—

tSYS_CLK_IN

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2]

and CFG_CLKIN_DIV) with respect to negation of PORESET when the

device is in PCI agent mode

4—

tPCI_SYNC_IN

Input hold time for POR configuration signals with respect to negation of

HRESET

0—

—

Time for the device to turn off POR configuration signal drivers with respect

to the assertion of HRESET

—4

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